SoC FPGA Interface Entwicklung

Design der Schnittstellen zwischen FPGA Soft-IP und (HPS/PS) Hard-IP auf der Hardware- und Softwareseite in jeglicher Art und Weise.

Erfahrung mit FPGA Soft- und Hard-IP Interfaces

• Low Speed Hard-IP (e.g. SPI, CAN,...)
• PCIe Hard-IP for PCIe Root-Complex End-Points (e.g. for FPGA PCIe Accelerator Cards)
• FPGA Transceiver Design (e.g. SFP+ 10Gbit Ethernet Interfaces)
• FPGA and HPS/PS Shared-memory SDRAM (DDR3, DDR4) Design
  with memory Optimization (SDRAM Calibration, SDRAM pre-loading, SDRAM Bank Interleaving, ...)
• Tightly Coupled Memory (TCM) Interfaces
• Soft-IP Interface Entwicklung with Arm® AMBA® AXI or Intel® Avalon® Bus Interfaces

Verwendete Design und Verification Tools und Technologien

• SystemVerilog, VHDL
• Intel® Quartus® Prime
• MentorGraphics® (Siemens® EDA) ModelSim™
• cocotb (for Python-based Testbench Design and Simulation)
• TCL- and Python-Scripts (for system verification, build automation,...)
• MathWorks® MATLAB™ (for Simulation input file generation)
• Arm® Entwicklung Studio (DS-5)
• HDL Soft-IP Timing Analyzation

Verwendete FPGA Device Familien

• Intel® Cyclone® V GX FPGA Family
• Intel® Cyclone® V SE/SX/ST SoC FPGA Family
• Intel® Arria® 10 SX SoC FPGA Family