FPGA HDL Design
Hardware Description Language (HDL) Designkompetenz mit selbstentwickelter Interface FPGA Soft-IP
- FPGA HDL Design and Synthesis
- Testbench Design and Simulation
- Intel® Nios® II Soft-Core Processor
- Intel® FPGA Memory (SDRAM) Optimization
- Partial Reconfiguration of the FPGA-Fabric
Verwendete HDL Design and Verification Tools
- SystemVerilog, VHDL
- Intel® Quartus® Prime
- MentorGraphics® (Siemens® EDA) ModelSim™
- cocotb (for Python-based Testbench Design and Simulation)
- Intel® External Memory Interface Toolkit (for the Intel® Arria® 10 SX)
- TCL- and Python-Scripts (for system verification, build automation,...)
- MathWorks® MATLAB™ (for Simulation input file generation)
- HDL Soft-IP Timing Analyzation
Bereits eigensetzte FPGA Familien
- Intel® MAX® 10 FPGA Family
- Intel® Cyclone® IV E FPGA Family
- Intel® Cyclone® V GX FPGA Family
- Intel® Cyclone® V SE/SX/ST SoC FPGA Family
- Intel® Cyclone® 10 LP FPGA Family
- Intel® Arria® 10 SX SoC FPGA Family
- Intel® Agilex™ 7 F-Series SoC FPGA Family